Lecture Notes


Text Books and Reference Materials


ÃÖº´À±, Verilog HDLÀ» »ç¿ëÇÑ µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ¹× ½Ç½À (IDEC °­Á ÀÚ·á)

ÀÌ°­, Àå°æ¼±, "Verilog-2001 µðÁöÅÐ ½Ã½ºÅÛ ¼³°è", È«¸ª°úÇÐ ÃâÆÇ»ç, 2009

½Å°æ¿í, "Verilog HDLÀ» »ç¿ëÇÑ µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ¹× ½Ç½À ", »çÀÌÅع̵ð¾î, 2009

¹ÚÀÎö, Core-A Computer Architecture & Design, È«¸ª°úÇÐÃâÆÇ»ç, 2009

Â÷¿µ¹è, "±âÃʺÎÅÍ ÀÀ¿ë±îÁö Verilog HDL", ´Ù´Ù¹Ìµð¾î

°­¼ºÈ£ ¿Ü 3¸í, HDLÀ» ÀÌ¿ëÇÑ SOC ¹× IP ¼³°è ±â¹ý, È«¸ª °úÇÐ ÁÙÆÇ»ç

Á¤Èñ¼º, µðÁöÅ» ȸ·Î ±â¼ú ¾ð¾î ÀÔ¹®

ÀåÈÆ ¿ª, "Verilog HDL", ¿µÇÑ ÃâÆÇ»ç

Cilette, "Advanced Digital Design with the Verilog HDL", PH

David J.Lilja, "Designing Digital Computer Systems with Verilog", Cambridge, 2005


HDL °ü·Ã Ãßõ Web sites



Note : Please use acroread 6.0 or newer version to print PDF file

Çϵå¿þ¾î ±â¼ú ¾ð¾î(HDL) : °­ÀÇ ÀÚ·á (±³¼ö ÇнÀ Áö¿ø ¼¾ÅÍ¿¡ µî·Ï )


IDEC °­Á ÀÚ·á(2009.1) : Verilog HDLÀ» ÀÌ¿ëÇÑ µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ¹× ½Ç½À(ÃÖº´À±)



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Last Modified March 2, 2012 by Byeong-Yoon Choi( bychoi@deu.ac.kr)