RISC-V and AI accelerator

• From Nand to Tetris (TextBook : The elements of computing system )

• From Nand to Tetris : courses (TextBook : The elements of computing system )

• From Nand to Tetris (TextBook : The elements of computing system ) : code ÀÚ·á(Github)

• From Nand to Tetris (TextBook : The elements of computing system ) : Q & A

• ¹Ø¹Ù´ÛºÎÅÍ ¸¸µå´Â ÄÄÇ»Æà ½Ã½ºÅÛ 2ÆÇ Ã¥ ºí·Î±× (TextBook : The elements of computing system ) : Q & A

• RISC-V Specification

• UC Berkeley Architecture Research

• RISC-V : Andrew Waterman Ph.D Thesis

• UC.Berkeley :Professor Krste Asanovic (homepage)

• UC.Berkeley :Professor Emeritus, David A. Patterson (homepage)

• Stanford :Professor John L. Hennesy (homepage)

• SiFive : RISC-V product (homepage)

• RISC-V Test (Github)

• RISC-V Toolchain (Github)

• 32-bit RISC-V Core(Verilog) (Github)

• higher performance dual issue CPU (RISC-V) with branch prediction RISC-V(BiRISC-V) Core(Verilog) (Github)

• UC Berkeley Architecture Lab : Setup scripts and files needed to compile CoreMark on RISC-V (Github)

• riscv-tools (Github) (ISA simulator, boot loader, riscv-test ..)

• RISC-V SoftCPU Contest(2018)

• Dhrystone: A Synthetic Systems Programming Benchmark

• CoreMark : An EEMBC Benchmark

• Rocket Chip Generator(Github)

• YARIV2 : in-order scalar RISC-V softcore with branch prediction (Github)

• WildCat : Educational RISC-V ±¸Çö (Github)

• WildCat : RISC-V ISA Simulator (Scala) (Github)

• RVSoC Project (homepage)

• Spike RISC-V ISA Simulator (Github)

• RISC-V Simulator (Rice Univ) (github)

• UC. Berkeley ´ëÇÐ EECS Çаú¿¡¼­ ¹ß°£ÇÏ´Â Technical Report (web sites)

• Stanford ´ëÇÐ CS Çаú¿¡¼­ ¹ß°£ÇÏ´Â Technical Report (web sites)

• ¼­¿ï´ë : RISC-V °­ÀÇÀÚ·á

• Cornell ´ëÇÐ : RISC-V °­ÀÇÀÚ·á

• RISC-V : IOb-SoC

• Stanford ´ëÇÐ Stanford Artificial Intelligence Laboratory

• synopsys : What is an AI Accelerator?

• KAIST Castlab : AI ACCELERATORS

• Tutorial on Hardware Accelerators for Deep Neural Networks

• DAF-MIT AI Accelerator

• Hailo-8 M.2 AI accelerator module

• AI accelerator IP Core

• The AI Accelerators Blog Series: a Year¡®s Retrospect

• AI Accelerator Computing Lab

• Xilinx FPGA °­Á : Xilinx Vivado Tool ±âº» »ç¿ë¹ý

• Xilinx Vivado Tool : Using Constraints