Current Research Project

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• Design of cryptographic and AI processor based on USB 3 Interface and Visual C# (2020-current, Internal research)

• Embedded Application using Arduino, Raspberry Pi Board and Jetson Nano Board (Internal research )

• AXI Bus Based SoC Design (2022-Current, Internal research )

• RISC-V Processor Design and Its Application to Embedded System (2022-Current Internal research )

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• Design of TCP/IP offload processor applicable to IoT (2015, Nexuschips)

• Design of VLIW Processor for Computer Vision (2013-2014, Nexuschips)

• Design of Tile-Based Rasterizer for Graphic Accelerator Core (2011-2012, Nexuschips)

• Design of OpenVG SW model on 3D graphics chips (2009 - 2010, Nexsuschips)

• Design of Unified Shader for 3-D Graphic Accelerator Core (2006 - 2008, Nexsuschips)

• Design of Texture Mapping Processor for 3-D Graphic Accelerator Core (2007, Nexsuschips)

• Design of Vertex Shader for 3-D Graphic Accelerator Core (2006-2007, Nexsuschips)

• Symmetric Key Cryptographic Processor for RFID and USN (2005, KISA)

• Design of Inruction-Path Coprocessing Processor (2004, Internal Funding)

• Versatile Public Key Cryptographic Processor (GF(2^n) ECC) (2004, ETRI)

• High-Speed RC4 Processsor Design (2004, Dong-Eui University Project)

• High-Speed RISC Processor for TCP/IP Stack Processor Core (2003, System IC 2010 Project)

• HDL Modeling of IPSEC Cryptographic Processor (2002, Glotrex )

• Design of Java Accelerator ( RISC Coprocessor for Smart Card Application) (2002, ETRI )

• Design of MD5, SHA, HAS-160 Hash Processor Design (2002, System IC 2010 Project)

• Design of AES, TDES, DES Symmetic-Key Processor(2001, System IC 2010 Project)

• Design of Universal GF(2^n) Inversion Circuit (2000. Dongeui University )

• Design of SEED Symmetic Key Encryption Processor (2000. Dongeui University + Secupia Inc.)

• Design of High Spped Symmetic Key Encryption Processor (2000. Dongeui University + Secupia Inc.)

• System IC 2010 Project : High Performance Embedded CPU / MCU Core Development (1999-2000, Dongeui, Yonsei, Samsung)

• VLSI Design of Encryption Processor (1999. Dongeui University)

• A Design of Controller for Cryptographic Coprocessor (1999. ETRI )

• VLSI Design of Systolic FFT Processor (1987, Yonsei University)

• VLSI Design of Pattern Matching Processor (1988, Yonsei University)

• Design Methodology of Self-Timed VLSI Circuit (1988, Yonsei University)

• VLSI Implementation of SPARC-Compatible RISC Microprocessor (1992, Yonsei University)

• VLSI Design of 32-bit RISC : SMART (1995, Dongeui University)

• VLSI Design of 32-bit RISC with 16-bit instruction and DSP multiplier : SMART-T (1997, Dongeui University)

• VLSI Design of 32-bit RISC for PDA Application (1998, Dongeui University)

• VLSI Design of Floating-Point Multiplier for Superscalar RISC Microprocessor (1996, Dongeui University)

• VLSI Design of Floating-Point Arithmetic Unit for Superscalar RISC Microprocessor (1996, Dongeui University)

• A Study on SRT Divider for Superscalar Microprocessor (1996, Dongeui University)

• VLSI Design of Adaptive Equalizer for Hard Disk Driver (1998, University of Illinois at Urbana-Champaign)

• VLSI Design of Viterbi Decoder for Hard Disk Driver (1998, University of Illinois at Urbana-Champaign)